The ability to dope polysilicon gates to different degrees allows one to adjust the work function of gate electrode materials to particular types of metal oxide silicon (MOS) transistors. It is desirable to adjust the work function of a gate electrode (hereinafter, the gate), to be close to either the conduction band or the valence band of silicon, because this reduces the threshold voltage (Vt) of the transistor, thereby facilitating a high drive current. For instance, dual work function gates are advantageously used in semiconductor devices, such as complementary metal oxide silicon (CMOS) transistor device, having both pMOS and nMOS transistors. The use of doped polysilicon gates becomes problematic, however, as the dimensions of gates and gate insulators are reduced.
Polysilicon gates can accommodate only a finite amount of dopants. This limitation can result in a depletion of gate charge carriers at the interface between the gate and gate dielectric, when the gate is biased to invert the channel. Consequently, the electrical thickness of the gate stack is substantially increased, thereby deteriorating the performance characteristics of the transistor, such as reducing the drive current and slowing switching speeds. For instance, the effective electrical thickness of a gate dielectric in some pMOS transistors can increase from about 1.0 nanometer during accumulation mode, to about 1.8 nanometers during inversion mode. Depletion of the polysilicon gate is a fundamental issue that limits further scaling of MOS devices.
In addition, when high-k gate dielectrics are used with polysilicon a Vt offset of up to 700 mV is observed for pMOS devices. This offset is associated with dopant, boron, diffusion and interaction with the gate dielectric. At present, there is no effective way to control for this Vt offset problem.
Metal gates are an attractive alternative to polysilicon because they have a larger supply of charge carriers than doped polysilicon gates. When a metal gate is biased to invert the channel, there is no substantial depletion of carriers at the interface between the metal gate and gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate stack is not increased. The manufacture of semiconductor transistors having adjustable dual work function metal gates has been troublesome, however.
Ideally, dual work function metal gates should be compatible with conventional gate dielectric materials and have suitably adjustable and stable work functions. It is challenging, however, to find such metals. For instance, there have been attempts to use fully nickel silicided polysilicon as the gate for MOS transistors, with implanted dopants used to adjust the work function. During the annealing process to fully silicide the gate, however, the implanted dopants can interact with the gate dielectric. This can result in the same type of Vt offset problem encountered for doped polysilicon. There is also the potential for nickel atoms to migrate into the gate dielectric and channel, thereby introducing defects that can degrade the performance, reliability, and stability of the device over time.
Others have attempted to use a hafnium nitride gate on a hafnium oxide gate dielectric. Such a gate has a mid-gap work function, meaning that the work function is about mid-way between the valence band and the conduction band of the substrate. Such mid-gap materials are unsatisfactory in a CMOS device, or other settings, where it is desirable to adjust the work function, in order to achieve a low Vt.
Accordingly, what is needed in the art is a method of manufacturing semiconductor devices having adjustable and stable metal electrodes.